举一个简单的例子：

//------------------------------------------------------------------------------------ // The following is an example of an inferred bidirectional bus in a Verilog design: //------------------------------------------------------------------------------------ module bidir_infer (DATA, READ_WRITE); input READ_WRITE ; inout [1:0] DATA ; reg [1:0] LATCH_OUT ; always @ (READ_WRITE or DATA) begin if (READ_WRITE == 1) LATCH_OUT <= DATA; end assign DATA = (READ_WRITE == 1) ? 2'bZ : LATCH_OUT; endmodule

其中，DATA为双向IO，则Testbench应做如下处理：

//------------------------------------------------------------------------------------ // The Verilog testbench can be set up as follows: //------------------------------------------------------------------------------------ module test_bidir_ver; reg read_writet; reg [1:0] data_in; wire [1:0] datat, data_out; bidir_infer uut (datat, read_writet); assign datat = (read_writet == 1) ? data_in : 2'bZ; assign data_out = (read_writet == 0) ? datat : 2'bZ; initial begin read_writet = 1; data_in = 11; #50 read_writet = 0; end endmodule

应当注意的是当read_writet的值与实际操作不一致是，所获得值应为Z！

注：例子中省略了timescale。